Power consumption is a major concern in modern electronics and processor-based devices. In recent years, the use of laptop and notebook computers for mobile computing has become commonplace. Also, personal digital assistants, or PDAs, are becoming a standard accessory for the busy professional. Moreover, many of today's mobile, cellular telephones include PDA functionality as a standard feature so that the user can access email, play computer games, or access the internet while on the move. In all of these examples, the electronic device relies on a finite power source, such as a battery. Thus, reducing power consumption, and thereby increasing battery life, is an important factor in fielding a product that is attractive to the market, and thus economically profitable.
One approach to reduce power consumption in a processor-based device is to reduce the current consumption of the processor. A common technique is to disable unused functional blocks within the processor based on the operation or set of operations being performed at a given time. Furthermore, the procedure for enabling and disabling functional blocks is inherently dynamic, as the blocks should be enabled so as not to introduce any processing latency, and yet be disabled quickly to minimize excess current use.
One of the most common techniques to enable and disable functional blocks is through “clock gating.” A “clock enable” signal can be used to “gate” a functional block's input clock to be in either an ON state or an OFF state. From a Boolean logic perspective, the clock enable can be viewed as being either a logic-1 or logic-0 that is ANDed with the clock input. If the clock enable is set to logic-1 (enable), then the value of the clock input passes unimpeded to the functional block. If the clock enable is set to logic-0 (disable), then the value of the clock input is forced to logic-0 as well, and is not able to clock any of the gates residing within the corresponding functional block.
Typically, as seen in the art, the clock enable for a particular functional block is generated by the functional block or blocks preceding it in the processing stream, or “pipeline.” This sequential approach attempts to provide the dynamic switching needed to reduce power consumption without introducing processing latency, as described above. However, because the clock enable for a given functional block is often generated by the preceding “upstream” functional block, the timing of the clock enable becomes a critical design constraint. For example, due to setup and hold time requirements, the upstream block may need to determine, or predict, whether or not a downstream block needs to be enabled before the time that the downstream block is to actually begin processing. If the upstream block decides in error, the downstream block may be enabled unnecessarily, thereby increasing the current consumption of the processor. Or, if there is a delay between the upstream block generating the enable and the time the downstream block needs to be activated, a processing latency can result that will impact the efficiency and speed of the processor, or worse, cause the processor to operate in an erroneous manner.
In some circumstances, an upstream block may itself be disabled when a downstream block is to be enabled. For example, if there are feedback loops in the hardware architecture, it may be that the upstream block must be re-enabled so as to enable the downstream block even if the upstream block does not need to perform any processing. In these cases, the common sequential clock enable circuitry usually must be augmented by potentially more complex circuitry to effectively enable and disable blocks that exist along the feedback path.